1. Field of the Invention
This invention relates to integrated circuits and more particularly to a method of invoking a power-down or reset mode on an integrated circuit.
2. Description of the Prior Art
In modern electronic systems, there is an increasing awareness of the need for or desirability of power conservation for many applications. Such systems require that their components have very low power consumption, or that the system have a power-down or standby mode where the power consumption can be reduced when the components are not in use. A signal must be received by these components to invoke this power-down or standby mode. Integrated circuits (IC) for such systems are generally contained in packages having standardized pin layouts, such as 16 pin dual in line (DIP), 8 pin DIP, pin grid arrays etc., with costs generally proportional to the number of pins, and with every pin utilized. Frequently, such power sensitive applications are also size-sensitive, as for example, in the case of portable equipment. The number of pins is usually limited on smaller packages, so that it may not be possible to have a dedicated power-down pin on the component. In such cases, it is required for the power-down or standby circuit to share a pin with another function.
One method of enabling a single device input pin to share two signals is to use multiple logic levels as described in pending U.S. patent application Ser. No. 08/627,504 of Ashe et al, filed Apr. 4, 1996, issued Feb. 3, 1998 as patent assigned to Analog Devices Inc., entitled "A three state logic input," incorporated by reference. Standard logic signals have two states--high (typically +5V) and low (typically 0V). By using a third level between these two (or even above logic high or below logic low), an additional signal, such as a power-down request, can be transmitted to the part. This arrangement presents some limitations. Firstly, the main signal on the pin (using the standard logic levels) must be inactive when the additional signal is being asserted. This is not however a problem if the additional signal is a power-down request, as most other signals would be ignored during power-down. Secondly, the arrangement requires additional circuitry--a window comparator to detect the presence of the new logic level, and also some form of timer circuit to determine if and when the new logic level has been asserted, and ensure that the comparator is not simply responding to a normal transition between two standard logic levels. Thirdly, a third logic level can be difficult to generate. A convenient manner of providing the third logic level is to have a weak voltage divider on the component between its supplies, which pulls the pin to the third logic level if the input is floated, but otherwise allows the input to be driven as normal. However, adding such a circuit may cause problems for inputs that are sensitive to impedance, such as a pin used for an external clock in/crystal oscillator function.
A second method of sharing signals to execute the power-down function has been used by Linear Technology Corp. This uses a combination of special sequencing on one pin plus holding a clock pin low to put a circuit in one of two power-down modes. A disadvantage of this system is that extra complexity is added to the application system by virtue of the need to apply this special sequencing, while also, since the circuit uses a combination of signals to invoke the power-down, there is an intrinsic requirement for two pins to be utilized. As noted above, this is not always a possibility, especially where package sizes are small and the number of pins available is limited.
A third method of implementing low power operation has been used by Maxim Integrated Products in a system which switches between a high speed comparator and a low speed power saving comparator. The input to the circuit is monitored. When no input signal is detected, operation is automatically switched from a high speed comparator to a low power comparator, which reduces the power consumption of the circuit. When the input signal becomes active again, the comparator is switched back to high speed operation. The method provides a power saving operation only and its implementation is dependent on the input signal.